The present invention relates, in general, to the field of multi-processor computer systems. More particularly, the present invention relates to a system and method for dynamic priority conflict resolution in a multi-processor computer system, for example a symmetric multi-processing ("SMP") computer system, having shared memory resources.
SMP is defined as the connection of more than one homogeneous processor to a single, monolithic central memory. However, until recently, hardware and software limitations have minimized the total number of physical processors that could access a single memory efficiently. These limitations have reduced the ability to maintain computational efficiency as the number of processors in a computer system increased, thus reducing the overall scalability of the system. With the advent of faster and ever more inexpensive microprocessors, large processor count SMP systems are becoming available and hardware advances have allowed interconnected networks to multiplex hundreds of processors to a single memory with a minimal decrease in efficiency.
Nevertheless, in any computer system that employs multiple processors which share the same memory space, it is possible that at least two processors may try to access the same memory simultaneously. In this instance a "conflict" is said to exist. In addition to memory, conflicts may also arise for any single element in the system wherein multiple users may require substantially concurrent access. An example of this type of conflict might occur when a port on a crossbar switch is used to route incoming signals from multiple ports to a selected output port; also a situation requiring conflict resolution. To resolve such conflicts, special circuitry must be added to the computer system in order to determine which device is allowed to access memory or another system resource at any given time.
The simplest of these circuits merely assigns a predetermined priority value to each of the processors in the system, when a conflict occurs, the circuit grants access to the highest priority processor. Any other processor must try to access memory at a later time, which causes it to be delayed. Although this circuit is easy to implement, it has a major drawback. It is possible for a single, high-priority processor to continually access the resource and prevent lower priority processors from ever getting access to it. This event will stall out the other processors and greatly reduce system performance. Also, as the number of processors increase, so will the likelihood of this event happening. As a result, it has been very difficult to build shared memory computers with hundreds of processors and still have the performance of that system scale well beyond 64 processors.